Khorakiwala2021_Chapter_P-typeCrystallineSiliconSurfac-solarbe文库

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P-type Crystalline Silicon Surface Passivation Using Silicon Oxynitride/SiN Stack for PERC Solar Cell Application Irfan M. Khorakiwala, Vikas Nandal, Pradeep Nair, and Aldrin Antony 1 Introduction Conventional p-type crystalline silicon-based solar cell technology uses aluminum back surface field for passivating the backside. The surface recombination velocity is very high compared to that of thermally grown silicon oxide passivation. Aluminum oxide grown by plasma-assisted atomic layer deposition ALD gives the best surface passivation [1]onp-type silicon, but employing these ALD processes on large scale is very challenging, and also, the deposition rate is very low. So in light of this, we try a relatively non-ideal passivation mechanism on the backside of p-type-based silicon wafers by hydrogenated silicon oxynitride SiO x N y H, from now on will be referred to as simply SiON layer with silicon nitride Si x N y , from now on will be referred to as simply SiN capping layers. These layers can easily be deposited on large scale using plasma-enhanced chemical vapor deposition PECVD at low temperature with high deposition rates. Additionally, the SiON layer has low refractive index less than 2 and their refractive index can be easily tuned [2] by changing the N 2 O precursor gas flow rates during deposition. These low refractive index values help SiON to become good IR reflectors at the rear side of the cell, which can boost the short-circuit current in solar cells. In light of this, we have tried to study how the passivation mechanism of SiON/SiN stack can be improved by extracting important information like fixed charge, mobile charge, and interface charge density using low- and high-frequency capacitance–voltage C-V measurements. We have also looked into the carrier lifetimes associated with such samples and tried to correlate the effect of these charges on the resulting carrier lifetime. SiN capping layers were deposited on the SiON layer, and the influence of this capping layer on the different types of charges in the dielectric is studied. I. M. Khorakiwala B · V. Nandal · P. Nair · A. Antony Department of Electrical Engineering, Indian Institute of Technology Bombay, Powai, Mumbai, Maharashtra 400076, India e-mail imkhorakiwalaiitb.ac.in © Springer Nature Singapore Pte Ltd. 2021 M.BoseandA.Modieds., Proceedings of the 7th International Conference on Advances in Energy Research, Springer Proceedings in Energy, https//doi.org/10.1007/978-981-15-5955-6_118 1237 1238 I. M. Khorakiwala et al. 2 Fabrication Details The SiON and SiN layers were deposited using plasma-enhanced chemical vapor deposition PECVD using Plasmalab 100 Oxford. We made three sets of samples with different compositions of SiON layers with different oxygen to nitrogen ratios by varying the N 2 O gas flow rates during deposition. We also made another sample withSiON/SiNstackasthedielectricpassivationlayertodemonstratetheimportance of the SiN capping layer. All the films were deposited at a temperature of 380 °C at an rf power density of 61.7 mW/cm 2 . All the SiON dielectric films have a thickness of 100 nm, and in the case of double stack the SiON layer is 30 nm thick and the capping SiN layer is 70 nm thick. The precursor gases used for SiON deposition are silane SiH 4 , hydrogen H 2 , and nitrous oxide N 2 O. Different compositions of oxygen and nitrogen were incorporated by fixing the silane flow rate to 15 sccm, hydrogen flow rate to 20 sccm, and varying the nitrous oxide gas flow rate. Three different N 2 O flow rates used are 45, 60 and 135 sccm. The gas mixture ratio Rof the SiON deposition is given by R SiON ∅ N 2 O ∅ N 2 O ∅ SiH 4 1 where ∅ SiH 4 and ∅ N 2 O are the gas flows of SiH 4 and N 2 O, respectively, in sccm. The sample names of the silicon oxynitride films can be represented as SiOxNy_R SiON where R SiON has the values 0.75, 0.8, and 0.9. The SiON layers are deposited at a pressure of 700 mTorr. The silicon nitride layer was deposited using 25 sccm of silane, 980 sccm of nitrogen, and 20 sccm of NH 3 . The SiN layer was deposited at a pressure of 650 mTorr. All these depositions were done over p-type 100 crystalline silicon wafer after the wafers were RCA standard cleaning process RCA 1 and RCA 2 cleaned. Before the deposition, the wafers were dipped in 2 HF solution to remove the native silicon oxide from the surface. We made “MOS capacitor”-type structures by depositing SiON single layer and SiON/SiN stack on the p-type substrate followed by front using shadow mask and backsideblanketlayermetaldeposition.Fourdifferent“MOScapacitor”-likestruc- tures named as samples A, B, C, and D were fabricated. Samples A, B, C, and D have different dielectric insulating layers, namely SiON 0.75, SiON 0.8, SiON 0.9, and SiON 0.9/SiN stack. On these test structures, we performed high- and low-frequency C-V measurements using Proxima Fast IV measurement/B1500 tool. The obtained C-V data were used to quantify the amount of fixed D f , mobile D m , and interface trap D it charge density in these dielectric layers when contacted with the p-type silicon substrate. For measuring the carrier lifetime, we deposited SiON single layers and SiON/SiN stack layer on both sides of the silicon substrate and carried out the carrier lifetime measurement using quasi-steady-state photoconductance QSSPC method using a Sinton WCT 120 tool. P-type Crystalline Silicon Surface Passivation 1239 3 Results and Discussions In order to understand the passivation mechanism of the dielectric layers, capac- itance–voltage C-V measurements were carried out at room temperature at four different frequencies 1 kHz, 10 kHz, 100 kHz, and 500 kHz to see the effects of fixed charge D f , in the dielectric layer close to the c-Si interface, mobile charge D m , in the dielectric layer, and interface charge D it , at the dielectric/c-Si interface on the passivation quality of the different SiON layers and particularly on one of the SiON_0.9/SiN stack. The fixed and interface charges originate because of dangling bonds or defects but the nature of these defects can be different. The fixed charge in SiON is predominantly known to be positive [3] as is the case with SiN. Fixed charge in the oxide shifts [4] the flat-band voltage of the C-V curve in one direction depending on whether the fixed charge is positive or negative. The amount of shift depends on the position of the fixed charge from the dielectric/c-Si interface. The amount of fixed charge introduced in the dielectric also depends on the type of deposition used. The flat-band voltage of the C-V curve also shifts by the presence of mobile charges in the dielectric. These mobile charges are basically ions moving through interstitial sites under the influence of the applied electric field. The interface charges at the dielectric/c-Si interface also shifts the flat-band voltage of the C-V curves and also stretches the C-V curve depending on the charge occupancy of the interface defect states, which is dictated by the position of the Fermi energy level as the voltage is applied. Now, we discuss the C-V data obtained for our samples Samples A, B, C, and D. The capacitance–voltage measurements in the forward and reverse sweep directions for four different frequencies are shown in Fig. 1 and Fig. 2, respectively. The x-axis of these plots is labeled as V top which means that the voltage was applied to the gate electrode with the back electrode at ground potential. From Figs. 1, 2, we see that the flat-band voltage of each of these samples is highly negative. Since the flat-band voltage has shifted in the negative direction, the polarity of fixed charge in these layers close to the c-Si interface is positive. Samples A, B, and C have higher fixed charge density D f compared to sample D. To calculate the fixed charge density in these samples, we measured the shift in flat-band voltage Delta1V FB compared to the ideal case when there are no charges no mobile, fixed, and interface charges at all in the dielectric layers. When there are no charges in the dielectric layer, the flat-band voltage in that case is simply the difference in work function Phi1 MS between the gate metal and the p-type silicon substrate. For our case, the gate metal used was aluminum with a work function of 4.1 eV and the substrate doping used was 10 16 cm −3 ; in this case, Phi1 MS turns out to be −0.83 V. The shift from this value is what determines the amount of fixed charges in these dielectric layers. The C-V plots in the forward Fig. 1 and reverse Fig. 2 sweep directions show hysteresis clearly indicating the presence of mobile charges in the dielectric layer. The amount of mobile charge density was calculated based on the difference in flat- band voltage Delta1V FB in the forward and reverse voltage sweep directions at a given frequency; here, we have calculated the mobile charge density at 1 kHz. The formula 1240 I. M. Khorakiwala et al. Fig. 1 Comparing C-V plots of four samples at four different frequencies during forward voltage sweep Note that the voltage range for sample D is from −10 to 10 V shown in blue used to calculate the mobile charge density D m can be seen in Fig. 4. The presence of mobile charge can be seen clearly in Fig. 3 where we have shown the hysteresis at a frequency of 1 kHz. The interface trap density D it was calculated by using the information obtained from both low-frequency 1 kHz and high-frequency in our case, 10 kHz C-V data. The obtained values for four different samples are shown in Fig. 4. The flat-band capacitance and interface trap charge density were calculated using the following set of formulas L D radicalBigg ε s V t qN A 2 C FB 1 1 C ox L D ε S 3 C ox ε ox t ox 4 D it C ox C LF C ox −C LF − C ox C HF C ox −C HF qA 5 P-type Crystalline Silicon Surface Passivation 1241 Fig. 2 Comparing C-V plots of four samples at four different frequencies during reverse voltage sweep Note that the voltage range for sample D is from −10 to 10 V where L D is the Debye length of holes, q is the charge, V t is the thermal voltage, N A is the acceptor boron concentration, C ox is the “oxide” capacitance which in our case is the dielectric layer capacitance, ε S is the electric permittivity of the c-Si base wafer, ε ox is the electric permittivity of the dielectric layer, C LF and C HF are the capacitances at low 1 kHz and high 10 kHz frequency, respectively, and A is the area of the “MOS” capacitor. All capacitances are expressed in terms of capacitance per unit area. Now to summarize the three different types of charges explored we refer you to Fig. 4. It can be seen that the fixed charge density peaks at sample C, i.e., SiON_0.8 and from then on falls off. In the case of sample D, the fixed charge density is the least; note that the fixed charge density for sample D cannot be seen in Fig. 4 as the density is too low for it to be shown in this figure. This reduction in fixed charge can be attributed to the SiN capping layer. The reason for this improvement in passivation is that during the plasma deposition of silicon nitride a large amount of hydrogen is released which helps in passivating many surface and bulk defects. This reduction in fixed charge is a boost to the majority holes in the p-type substrate near the SiON/c-Si interface which were earlier facing an opposing electric force due to the positive fixed charges which explains why the flat-band voltage of the dielectric stack capacitor is much lower compared to the single SiON layer capacitors. The mobile charge 1242 I. M. Khorakiwala et al. Fig. 3 Hysteresis obtained at 1 kHz between the forward and reverse voltage sweep direction for four different samples Fig. 4 Extracting the non-ideal charges in the four different dielectric layers Note D t corresponds to the total positive charge P-type Crystalline Silicon Surface Passivation 1243 Table 1 Lifetime and implied V oc of p-type c-Si wafer with dielectric passivation layers deposited on both sides of the silicon wafer Sample name Lifetime µs Implied V oc SiON_0.75 52.1 621 SiON_0.8 48.3 620 SiON_0.9 30.6 608 SiON_0.9/SiN 64.7 627 density is highest for sample D and lowest for sample C. The higher mobile charge density of sample D could be because the SiN layer is denser than the SiON layer, and hence, the mobile carriers are mostly centered in the bulk of the SiON layer. The interface trap charge density is highest for sample B and least for sample D.The reduction of D it for sample D is again because of the hydrogen passivation which reduces the interface dangling bonds and this hydrogen comes from the SiN capping layers during their plasma deposition. The carrier lifetime and implied V oc of c-Si passivated on both sides by four different dielectric layers are shown in Table 1. For single SiON layers as the N 2 O flowrateisincreased,thepassivationpropertybecomesmoreandmoreinferiorascan be seen from Table 1. In the literature, Zhuo et al. [5] have reported that incorporating more nitrogen into the SiON layers degrades the passivation quality of these layers. The passivation quality obtained when a dielectric stack of SiON_0.9/SiN is used instead of single SiON_0.9 layer is significant as can be seen from Table 1.The reason for this improvement in passivation was discussed earlier. The D it calculations and the above-listed lifetime are in close agreement to one another, and hence, the impact of interface state trap density is most significant compared to the other kinds of charges discussed in this work. 4 Conclusion In this paper, we explored the possibilities of SiON/SiN as backside passivating dielectrics for p-type crystalline silicon substrates SiON/SiN act also as good antire- flective coatings for infrared photons as these layers can be deposited easily on large scale using PECVD at low temperatures and at high deposition rates. We have quantified three different types of charges predominant in these dielectric insulators, namely fixed charge, mobile charge, and interface trap charge. These charges were calculated from the low- and high-frequency capacitance–voltage measurements of the “MOS” like capacitor structures incorporating four different dielectric insula- tors SiON_0.75, SiON_0.8, SiON_0.9, and stack of SiON_0.9/SiN. It is found that incorporating more nitrogen during the PECVD deposition is detrimental to the interface passivation between crystalline silicon and the dielectric layers as is evident from the carrier lifetime measurements Table 1 and the calculated interface charge density Fig. 4. We demonstrated the importance of the SiN capping layer which helps in reducing the interface charges and also the positive fixed charges in 1244 I. M. Khorakiwala et al. the SiON_0.9 layer after it is capped. The benefits of SiN capping layer are that during its plasma depositi